A Practical Nonbinary Decoder for Low-Density Parity-Check Codes with Packet-Sized Symbols

This paper presents a practical decoder for regular low-density parity-check (LDPC) codes with flexible packet-sized symbols. The proposed hMP-VSD (Combined hard-decision message-passing with vector symbol decoding) is much less complex than the conventional VSD and has the same decoding performance. Regular LDPC codes with systematic encoding are selected for implementation. The channel is assumed to be the q-ary symmetric channel (q-SC). Different code lengths and column weights of LDPC codes are investigated. The results show that the codes with a column weight of 7 provide the best performance for hMP-VSD, while hMP works best with codes having a column weight of 5. With packet-sized symbols, even the rather short (60, 30) code structure has code lengths of 1,920 to 245,760 bits with symbol sizes of 32 to 4,096 bits. Both the decoder and its encoder were implemented on Raspberry-pi 4 model B boards and these results confirm that the computation time of hMP-VSD is 60% to 70% lower than that of VSD for pe in the range 0.05 to 0.1

Verification-Based Decoding for Rateless Codes in the Presence of Errors and Erasures

In this paper, verification-based decoding is proposed for the correction and filling-in of lost/erased packets for multicast service in data networks, which employs Rateless codes. Patterns of preferred parity-check equations are presented for the reduction of the average number of parity-check symbols required. Since the locations of unverified symbols are known, the effect of erasures and errors is the same in terms of the overhead required for successful decoding. Simulation results show that for an error-only, an erasure-only or a combination of both at 10% error/erasure probability, 78% of the messages can be recovered with a 50% overhead, whereas 99% of the messages can be recovered with a 100% overhead